The
switched charge multiplier-divider according to the present
invention is constructed of CMOS devices. Capacitor charge theory
is employed to implement the circuit of the switched charge
multiplier-divider. The switched charge multiplier-divider includes
an output capacitor and controls the voltage across the output
capacitor, so that it is proportional to the product of the
charge current and the charge-time interval. The switched charge
multiplier-divider is ideal for use in the power factor correction
(PFC) of switching mode power supplies. Potentially, it can
also be applied to automatic gain control (AGC) circuits.
中文摘要
本發明提出一種切換式充電的乘-除法器，係由互補式金屬氧化半導體(CMOS)所構成，並且應用電容充電原理來實現。該乘-除法器依據第一乘法器輸入訊號、第二乘法器輸入訊號與除數輸入訊號這三個輸入訊號而產生一輸出電壓訊號。該輸出電壓訊號係正比於第一乘法器輸入訊號與第二乘法器輸入訊號的乘積；該輸出電壓訊號係反比於除數輸入訊號。該切換式充電的乘-除法器包含一輸出電容，並藉由使用一充電電流與一可規劃充電時間進行切換該輸出電容，使得跨於該輸出電容上的電壓可以得到控制。該輸出電容上的電壓即為切換式充電的乘-除法器的輸出電壓。如此一來，跨於該輸出電容上的電壓就會正比例於充電電流與可規劃充電時間的乘積。該切換式充電的乘-除法器不僅適用於切換式電源供應器之功因修正(PFC)電路，更可應用於自動增益控制(Automatic
gain Control, AGC)電路。
專利特色
此乘除器可有效改進輸入雜訊影響，增加雜訊免疫力。
專利字號
US6,812,769
專利內容
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英文摘要
