The
switched charge multiplier-divider according to the present
invention is constructed of CMOS devices. Capacitor charge theory
is employed to implement the circuit of the switched charge
multiplier-divider. The switched charge multiplier-divider includes
an output capacitor and controls the voltage across the output
capacitor, so that it is proportional to the product of the
charge current and the charge-time interval. The switched charge
multiplier-divider is ideal for use in the power factor correction
(PFC) of switching mode power supplies. Potentially, it can
also be applied to automatic gain control (AGC) circuits.
Highlight
This
invention greatly improves signal noise resistance .
Abstract 
